High-Speed Counter Module Overview

The High-Speed Counter Module, Catalog Number 1746-HSCE is an SLC 500 family

compatible device except with the 1747-ASB Remote I/O Adapter Module. It can be

used with SLC™ 5/02 (and above) processors.

The module’s bidirectional counting ability allows it to detect movement in either

direction. In addition, x2 and x4 counting modes are provided to fully use the

capabilities of high-resolution quadrature encoders.

High-speed inputs from quadrature encoders and various high-speed switches are

supported. Accepting input pulse frequencies of up to 50k Hz allows precise

control of fast motions.

In addition, an Accumulated Counter, the module provides a Rate Counter to

determine Rate Measurement by indicating the pulse input frequency in Hz. (See

the block diagram on page 6.) The Rate Measurement is determined by

accumulating input pulses over a fixed period of time. You set the Rate Period to

best match your application requirements.

Background Rate calculation is provided in Sequencer and Range Modes. This

operation accepts input rates up to 32,767 Hz. The dynamically configurable Rate

Period ranges from 10 ms to 2.55 seconds.

The module’s four current sink (open collector) outputs can be controlled in the

user program or the module.

Control of the counter reset is configured through user-set parameters. The counter

can be reset from any combination of the Z input, Limit Switch input, or Soft Reset control bits.

Module operation is determined by selections made in the Setup and Control Word

(M0:e.1). Setting the Function Control bit to 1 triggers the module to start the

proper pulse counter, rate measurement, www.abb-drive.com and output control functions. Many

parameters are dynamic and can be changed without disrupting counter operation.

The module’s block diagram is shown on page 6. Inputs from the terminal block

enter the diagram at the left, outputs to the terminal block exit at the right. M0 and

Output file parameters from the SLC enter the logic blocks from the top. Input file

data to the SLC exit the logic blocks from the bottom.